Signal processing system for reducing power consumption

ABSTRACT

A low power audio processor is disclosed which includes a bit stream processing unit for performing bit processing for an applied audio stream and for decoding the bit processed audio stream to have a format conducive to digital signal processing; a digital signal processing unit for receiving the decoded data from the bit stream processing unit to perform digital signal processing; a post processing unit for post processing audio data from the digital signal processing unit to output final audio data; and a host interface unit for interfacing with an external device to provide an audio parallel stream from the external device to the bit stream processing unit. The audio signal processor also includes a power control unit for determining the idle state for each of the bit stream processing unit, the digital signal processing unit and the post processing unit in response to: (a) a request signal and an acknowledge signal between the digital signal processing unit and the post processing unit, (b) a power down signal, and (c) a source clock to output the determined power state as a power mode signal; and an internal clock signal generator for generating clock signals, in response to the power mode signal and for outputting the clock signals to respective one of the bit stream processor, the digital signal processor and the post processor.

FIELD OF THE INVENTION

[0001] The present invention relates generally to an audio signalprocessor, and, more particularly, to an audio signal processor having aplurality of sub-processing units which are only driven when currentlyneeded for processing.

BACKGROUND OF THE INVENTION

[0002] A conventional audio processor or signal processor digitallyprocesses an application program by using a signal processing unit,which leads the whole signal processing unit to be driven at every flow,causing power consumption of the processor to be very high. Especially,when a high performance program is processed at a high frequency,unessential parts of the hardware are driven, and more power isconsumed.

SUMMARY OF THE INVENTION

[0003] According to a preferred embodiment of the invention, a low poweraudio processor is provided that comprises: a bit stream processing unitfor bit processing an applied audio stream into a bit processed audiostream, and for decoding the bit processed audio stream to have a formatconducive to digital signal processing. A digital signal processing unitis also included for digital signal processing the decoded bit processedaudio stream from the bit stream processing unit to develop a digitalsignal processed audio stream. The audio processor further includes apost processing unit for receiving the digital signal processed audiostream from the digital signal processing unit to develop final audiodata. A host interface unit is included for interfacing with an externaldevice to provide an audio parallel stream received from the externaldevice to the bit stream processing unit. A power control unit isincluded for determining the power state for each of the bit streamprocessing unit, the digital signal processing unit, and the postprocessing unit in response to (1) a request signal and an acknowledgesignal between the digital signal processing unit and the postprocessing unit, (2) a power down signal and (3) a source clock, thepower control unit outputting a determined power state as a power modesignal. There is also an internal clock signal generator unit forgenerating clock signals in response to the power mode signal, each ofthe clock signals corresponding to a respective one of the bit streamprocessing unit, the digital signal processing unit, and the postprocessing unit.

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The following description of preferred embodiments refers to theaccompanied drawings, in which:

[0005]FIG. 1 is a block diagram of an exemplary audio processorconstructed in accordance with the teachings of the present invention;

[0006]FIG. 2 shows an internal state diagram of the PMU of FIG. 1; and

[0007]FIG. 3 offers an internal block diagram of the internal clocksignal generator of FIG. 1.

DETAILED DESCRIPTION

[0008]FIG. 1 is a block diagram of an exemplary audio processorconstructed in accordance with the teachings of the present invention.As shown in FIG. 1, the disclosed audio processor comprises a bit streamprocessing (BSP) unit 100 for bit processing of an applied audio streamto compress the audio stream. The BSP unit 100 also decodes the bitprocessed audio stream to a format amenable to digital signalprocessing. A digital signal processing (DSP) unit 110 receives thedecoded data in the digital signal processing format from the BSP unit100 and performs digital signal processing by using a digital signalprocessing algorithm. A post processing unit 120 receives audio datafrom the DSP unit 110 and performs further post processing, such asequalizing processing, and outputs final audio data.

[0009] A host interface unit 130 is also included to interface with anexternal device through a parallel bus and/or a serial bus. The hostinterface unit 130 transmits an audio stream from an external devicethrough the parallel bus to the BSP unit 100. The audio processor alsoincludes a power control unit (PMU) 140 for determining idle states foreach unit. The PMU 140 accomplishes this power control by using arequest signal and an acknowledge signal between the DSP unit 110 andthe post processing unit 120. These signals are generated in response toa power down signal PWRDN from outside and a source clock SOURCE_CLOCKto output the determined power state as a power mode signal.

[0010] The audio processor further includes an internal clock signalgenerator 150 for generating clock signals that correspond to each unitin response to the power mode signal to output each of the clock signalsto the corresponding units.

[0011] A program memory is also included in the audio processor, whichis coupled to the BSP unit 100, the DSP unit 110 and the post processingunit 120. The program memory 160 is driven by a memory clock MEM_CLKfrom the internal clock signal generator 150. The memory clock is drivenwhen the BSP unit 100, the DSP unit 110 and the post processing unit 120perform processing.

[0012] Still referring to FIG. 1, the BSP unit 100 performs the bitprocessing for the audio stream, analyzes the compressed data, and thenconverts the format of the compressed data to a format for digitalsignal processing. The DSP unit 110 performs typical audio algorithmprocessing and the post processing unit 120 outputs real time audiodata. Therefore, the request signal and the acknowledge signal aretransferred among the BSP unit 100, the DSP unit 110 and the postprocessing unit 120 to perform the processing sequentially in order ofthe BSP unit 100, the DSP unit 110 and the post processing unit 120,which confirms the start and end of processing that is performed at eachunit. The request signal and the acknowledge signal are applied to theinput of the PMU 140.

[0013] Since the idle state of each unit can be recognized from therequest signals and the acknowledge signals, the PMU 140 specifies thepower state based upon the request signals and the acknowledge signals.The PMU 140 then outputs the specified power state as the mode signal.

[0014] The internal clock signal generator 150 generates clock signalsBSP_CLK, DSP_CLK, POST_CLK, each of which is applied to one of thecorresponding units 100, 110 and 120, depending on the mode signal fromthe PMU 140. The clock signal generator 150 also generates the memoryclock MEM_CLK to enable the memory 160 when one of the units 100, 110and 120 performs a processing operation in response to a correspondingclock signal from the internal clock signal generator 150.

[0015]FIG. 2 shows an internal state diagram for the PMU 140 of FIG. 1.As shown in FIG. 2, the PMU 140 has three states; standby state, runstate and power off state.

[0016] The standby state is a default state after reset. In this state,the internal clock signal generator 150 and the host interface unit 130operate with a programmable clock of ½ of the source clock and the otherprocessing units remain in a static state.

[0017] The run state is a state in which the host interface unit 130performs parameter setup before a run command that is generated at thehost interface unit 130. The state of each unit is also monitored toperform clock masking. During this state, the fundamental clock remainsat ½ of the source clock and is divided by one, two or four asappropriate for the driven module.

[0018] Finally, when a power down pin is activated at the standby state,the state transits to the power off state in which the source clockbecomes DC.

[0019] In other words, when processing is required during the standbystate, (i.e., idle state), the run command is generated to transit tothe run state. After that, a standby command is generated to transit tothe standby state when the processing is ended. And, the standby statecan transit to the power off state in which power is turned off throughthe external power down pin. Therefore, power consumption is reducedsignificantly.

[0020]FIG. 3 offers a block diagram of the internal clock signalgenerator 150 of FIG. 1. The internal clock generating means 150includes a multiplexer 200 for selectively outputting one of a DC leveland the source clock in response to the power down signal PWRDN. Adivider 210 is included for dividing the output of the multiplexer 200by one, two or four, and three multiplexers 220, 230 and 240. Each ofthe three multiplexors selects one of the corresponding clock signalsapplied from the branch 210 and the DC level in response to the idlestate of the corresponding processing unit to output the selected signalto the corresponding processing unit.

[0021] Referring to FIG. 3, depending on the power state specified atthe PMU 140, the internal clock signal generator 150 provides separateclock signals to the corresponding units.

[0022] The multiplexer 200 blocks input from the clock by selecting theDC instead of the source clock SOURCE_CLOCK during a power off state(identified by the power down signal PWRDN). It outputs the source clockSOURCE_CLOCK in all other states. The branch 210 branches the sourceclock SOURCE_CLOCK depending on the power mode to generate the clocksignals for each unit.

[0023] After that, depending on the idle state of each processing unit,the clock signal branched at the branch 210 is applied to the BSP unit100, the DSP unit 110 and the post processing unit 120.

[0024] On the other hand, data processed at each of the processing unitsis temporarily stored at the memory device 160. As flow occurssequentially, data processed at the BSP unit 100 is the input of the DSPunit 110. Data that has then undergone digital signal processing at theDSP unit 110 is the input of the post processing unit 120. Therefore,the memory is driven by not only one of the processing units but by twoof the processing units. Because the clock signal MEM_CLK for drivingthe memory 160 cannot be used commonly with the clock for each unit, thememory clock MEM_CLK is separately generated by a logic device 250(i.e., an OR gate operating the clock signal BSP_CLK from the BSP unit100, the clock signal DSP_CLK from the DSP unit 10, and the clock signalPOST_CLK from the post processing unit 120) in the internal clock signalgenerator 150 as shown in FIG. 3.

[0025] As described above, the disclosed audio processing unit issubdivided functionally into the bit stream processing unit 100, thedigital signal processing unit 110, and the post processing unit 120 foraudio signal processing. Also, the power state of each unit 100, 110,120 is determined by analyzing the state of each unit 100, 110, 120 atthe power control unit 140. The internal clock signal generator 150 thengenerates clock signals depending on the determined power state to driveonly one of the three units 100, 110, 120. Therefore, the discloseddevice is capable of performing the application program by using adriving frequency that is about ½ to ⅓ of a conventional drivingfrequency so as to reduce power consumption of the audio processor.

[0026] While the teachings of the present invention have been explainedin connection with particular examples, it will be apparent to those ofordinary skill in the art that the scope of this patent is not limitedto those examples. On the contrary, this patent covers all structuresfully within the spirit and scope of the appended claims.

1-4. (cancelled)
 5. Apparatus for generating a plurality of controlclocks in response to a power state of a plurality of processing units,comprising: a first multiplexor for selectively outputting one of a DClevel and a source clock in response to a power down signal; a branchfor branching the output of the first multiplexor into a predeterminednumber of branches; and a plurality of multiplexors, each for selectingrespective ones of the clock signals from the branch and the DC level inresponse to the power state of a corresponding one of the plurality ofprocessing units and outputting the selected signal to the correspondingprocessing unit.
 6. The Apparatus as recited in claim 5, furthercomprising a logic device for AND operating the outputs of the pluralityof multiplexors to drive a memory device.
 7. A signal processing systemfor reducing power consumption, comprising: a plurality of processingunits; an internal clock signal generator unit for receiving a sourceclock and a power down signal and generating clock signals, each of theclock signals corresponding to a respective one of the plurality ofprocessing units.
 8. The signal processing system as recited in claim 7,wherein the internal clock signal generator unit includes: a firstmultiplexor for selectively outputting one of a DC level and the sourceclock in response to the power down signal; a branch for branching theoutput of the first multiplexor into a predetermined number of branches;and second, third and fourth multiplexors, each for selecting respectiveones of the clock signals from the branch and the DC level in responseto the power state of a corresponding one of the bit stream processingunit, the digital signal processing unit and to post processing unit,each of the second, third and fourth multiplexors outputting, a selectedsignal to a respective one of the bit stream processing, digital signalprocessing and post processing units to output the selected signal tothe corresponding processing unit.
 9. The system as recited in claim 8,wherein the internal clock signal generator unit includes a logic devicefor AND operating the outputs of the plurality of multiplexors to drivea memory device.